1. Technical Field
The embodiments described herein relate to a delay locked loop (DLL) circuit and a method for controlling the same, and more particularly, to a DLL circuit that can generate an internal clock signal whose phase is more advanced than a phase of an external clock signal and a method for controlling the same.
2. Related Art
In general, a DLL circuit is used to provide an internal clock signal whose phase is more advanced than a phase of a reference clock signal obtained by converting an external clock signal. The DLL circuit is also used to resolve the following problem: If an internal clock signal used in a semiconductor integrated circuit is delayed by a clock signal buffer and a transmission line, a phase difference is generated between the internal clock signal and an external clock signal, which results in an increased output data access time. As a result, in order to increase an effective data output period, the DLL circuit performs a control operation such that a phase of the internal clock signal is more advanced than a phase of the external clock signal by a predetermined amount.
The duty ratio of a DLL output clock signal should be maintained at a predetermined ratio (for example, 50:50) to prevent the deterioration of the operational efficiency of a DLL circuit. However, the duty ratio of the output clock signal from the DLL circuit can easily vary due to jitters outside the DLL circuit and irregular delay values of delay elements inside the DLL circuit. To prevent the duty ratio from varying, a conventional DLL circuit includes a duty cycle correction device to maintain a duty ratio of an output clock signal at a predetermined ratio.
However, a conventional duty cycle correction device included in a conventional DLL circuit occupies a wide area and has a long operation time, or an operational characteristic thereof is deteriorated when operating at low power. Due to the high-speed operation, high integration, and low power consumption of today's semiconductor integrated circuits, it has been required to implement a clock signal having an accurate duty ratio.